A Realizable Eecient Parallel Architecture

The near future will present large scale parallel computers, able to provide computing power of more than one TFlop per second. It is commonly agreed that these systems will be based on the model of asynchronous processors connected by a point to point network. There are a number of diierent network architectures presented in the past. In this paper we present an architectural principle that combines eeciency, realizability for very large systems, and inherent reliability needed for such large parallel processing systems. The here presented Fat Mesh of Clos network principle can be scaled in many ways to fullll the special requirements of a system design. Two realizations of this principle are presented: One is based on static switches combined to form a fully reconngurable system. This architecture has been realized for systems containing up to 320 processors. The other realization uses dynamic routing switches. By combining wormhole routing with randomized and local adaptive routing this network provides large capacity and very short latency times. The eeciency of our principle is demonstrated by simulations. Both realizations presented here are built and commercialized by Parsytec Computer.